1. Field of the Invention
The present invention generally relates to semiconductor devices, to power-on reset circuits for initializing an internal circuit of the integrated circuit device, and to a method of generating a power-on rest signal.
2. Description of Related Art
Power-on reset circuits (commonly referred to as “power-up detector circuits”) provide a reset signal for initializing flip-flops, latches, counters and other internal elements of a device such as a semiconductor integrated circuit when a power supply voltage is applied thereto. The reset signal is maintained at a first voltage (e.g., a logic “low” or “0”) at a given time sufficient for stabilizing each element in the semiconductor integrated circuit. After a given time elapses, the reset signal is inverted to a second voltage (e.g., a logic “high” or “1”) while the power supply voltage is applied to the semiconductor integrated circuit.
Various power-on reset circuits are disclosed in U.S. Pat. No. 4,788,462, entitled “POWER-ON-RESET (POR) CIRCUIT”, in U.S. Pat. No. 5,471,130, entitled “POWER SUPPLY CONTROLLER HAVING LOW STARTUP CURRENT”, in U.S. Pat. No. 5,519,347, entitled “START-UP CIRCUIT FOR STABLE POWER-ON OF SEMICONDUCTOR MEMORY DEVICE”, in U.S. Pat. No. 6,204,703, entitled “POWER ON RESET CIRCUIT WITH POWER NOISE IMMUNITY”, in U.S. Pat. No. 6,236,249, entitled “POWER-ON RESET CIRCUIT FOR A HIGH DENSITY INTEGRATED CIRCUIT”, in U.S. Pat. No. 6,346,834, entitled “POWER ON RESET CIRCUIT” and in KR Publication No. 2002-31843, entitled “POWER-UP CIRCUIT”.
FIG. 1 is a schematic block diagram of a semiconductor integrated circuit device with a conventional power-on reset circuit; and FIG. 2 is a graphic diagram illustrating an output signal of a power-on reset circuit shown in FIG. 1.
Referring to FIG. 1, the semiconductor integrated circuit device 10 includes a power-on reset (POR) circuit 20 and an internal circuit 30. The internal circuit 30 may be a conventionally-known integrated circuit which includes a switch SW, a latch LAT1 and a PMOS transistor M1. The switch SW includes a transmission gate TG1 receiving an input signal IN and a clock signal CLK to output a signal to the latch LAT1, and an inverter INV1 which receives the CLK at an input and outputs an inverted CLK signal to the transmission gate TG1. Latch LAT1 includes inverters INV2 and INV3, which receive the signal generated from TG1 of switch SW in order to generate an output signal OUT from the internal circuit 30. The latch LAT1 in the internal circuit 30 is initialized by an output signal VCCH of the POR circuit 20 at a power-on of the device 10. As illustrated in FIG. 2, when a power supply voltage VCC reaches a specified voltage Va during power-on, the output signal VCCH transitions from a low level to a high level. The latch LAT1 is initialized during an initialization interval. The duration of the initialization interval extends from a first time instant, when the power supply voltage VCC reaches a threshold voltage Vth of the PMOS transistor M1, to a second time instant when the power supply voltage VCC reaches the specified voltage Va.
The POR circuit 20 may be embodied, for example, by a differential amplifier, as illustrated in FIG. 2 of the above-noted '347 patent. The differential amplifier disclosed in the patent '347 generates a start-up signal transition at a specific time, regardless of a temperature variation. Even though the start-up signal transitions at a constant point of time despite the variations in temperature, the following problems may arise if an operation voltage or a power supply voltage becomes substantially low or is at a substantially low voltage.
In the following example, the output signal VCCH transitions from a low level to a high level when a power supply voltage VCC reaches 1.2V, a threshold voltage Vth of the MOS transistor is 0.5V, and the initial power supply voltage VCC is 0.7V. Accordingly, the PMOS transistor M1 in the internal circuit 30 of FIG. 1 is turned on only in a range of 0.5V to 0.7V. The turning-on range of the PMOS transistor M1 represents an initialization interval. The duration of the initialization interval is shortened if a rising gradient of the power supply voltage VCC is substantially sharp. In other words, this means that the start-up operation may not be performed in a normal manner. That is, as the power-supply voltage VCC decreases, it becomes increasingly difficult to adequately secure the initialization interval of the start-up signal.